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Microchip Technology /ATSAMV71J21B /USBHS /DEVEPTICR_ISO_MODE[6]

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Interpret as DEVEPTICR_ISO_MODE[6]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXINIC)TXINIC 0 (RXOUTIC)RXOUTIC 0 (UNDERFIC)UNDERFIC 0 (HBISOINERRIC)HBISOINERRIC 0 (HBISOFLUSHIC)HBISOFLUSHIC 0 (OVERFIC)OVERFIC 0 (CRCERRIC)CRCERRIC 0 (SHORTPACKETC)SHORTPACKETC

Description

Device Endpoint Interrupt Clear Register

Fields

TXINIC

Transmitted IN Data Interrupt Clear
RXOUTIC

Received OUT Data Interrupt Clear
UNDERFIC

Underflow Interrupt Clear
HBISOINERRIC

High Bandwidth Isochronous IN Underflow Error Interrupt Clear
HBISOFLUSHIC

High Bandwidth Isochronous IN Flush Interrupt Clear
OVERFIC

Overflow Interrupt Clear
CRCERRIC

CRC Error Interrupt Clear
SHORTPACKETC

Short Packet Interrupt Clear

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data